A conventional NAND flash memory device 100 includes multiple NAND strings of memory transistors. FIG. 1 illustrates two NAND strings of the conventional NAND flash memory device 100. To program a memory transistor 102, a selected bitline 1 is grounded by passing a bitline select voltage 104 of 0 volt through the drain of a drain select (DS) transistor 1 to a node of the memory transistor 102, while a bitline 2 and the rest of the bitlines are self boosted by coupling to a programming voltage 118 and/or a pass voltage 120 to inhibit the programming. A drain select (DS) line 108 and a source select (SS) line 110 are coupled to a node of a DS voltage 112 and to a node of a SS voltage 114, respectively. The supply voltage of the DS line 108 turns on the DS transistor 1 and maintains the connection of the bitline 1 to the bitline select voltage 104, but it turns off the DS transistor 2, thus disconnecting the bitline 2 from the bitline unselect voltage 106. The SS voltage 114 coupled to the SS line 110 turns off both the SS transistor 1 and the SS transistor 2, thus isolating the two bitlines from a node of a common source voltage 116 during the programming.
Furthermore, a wordline N coupled to the control gate of the memory transistor 102 is applied by the programming voltage 118 of 18 volts while the unselected wordlines are applied by the pass voltage 120 of 11 volts. Since the channel of the bitline 1 is coupled to the bitline select voltage 104 of 0 volt, it is maintained at the channel voltage of 0 volt, whereas the channel potential of the bitline 2 is coupled up by the programming voltage 118 and/or the pass voltage 120. For example, with the pass voltage 120 of 11 volts being supplied to the unselected wordlines, the channel voltage of the bitline 2 may range between 6 to 9 volts.
Before the programming takes place, the threshold voltage of the cell 102 is about −2 volt. When the programming voltage 118 is applied, the high voltage of the programming voltage 118 causes the tunneling of electrons from the silicon substrate of the memory transistor 102 to the charge trap layer of the memory transistor 102, thus increasing the threshold voltage to a positive voltage of 1 volt, whereas the voltage differential between the silicon substrate and the floating gate of each unselected cell is not large enough to cause the change in the threshold voltage of its respective transistor.
FIG. 2 illustrates an exploded view of a portion of the bitline 2 viewed across Y-direction which includes the SS transistor 2, a memory transistor 122 (e.g., coupled to an edge wordline, such as the wordline N), and a memory transistor 124. The SS transistor 2 controls the bitline 2 for connecting to a common source 202. Furthermore, the SS transistor 2 is 200 nm in size, the transistors 90 nm in size, and the channels 100 nm in size. The boosted junction potential between the SS transistor 2 and the memory transistor 122 may range between 6 and 9 volts, where the gate of the SS transistor 2 is grounded. Provided that the channel voltage for unselected bitline 2 being 6 to 9 volts, the gate voltage of the memory transistor 122 being 18 volts, and the gate voltage of the SS transistor 2 being 0 volt, there is a great disturbance with the band-to-band tunneling of the memory transistor 122. That is, the memory transistor 122 is disturbed by an electron hole pair (EHP) generation due to a gate induced drain junction leakage (GDIL) current.
The GIDL current arises in a high electric field under a gate junction overlap region and a low gate to drain bias. The GIDL current occurs when current flows from the junction 204 in direction to the substrate 208 under the gate junction overlap region, such as the overlap region of the gate of the SS transistor 2 and the junction 204. The GIDL is due to the formation of the depletion region and the region's high electric field in presence of the low or negative bias in the gate of the SS transistor 2 (e.g., 0 volt), and the positive bias in the junction 204 of the cell 122 (e.g., 6 to 9 volts). In the overlap gate junction region, the high electric field creates electron-hole pairs (EHPs) where electrons through the barrier height are collected by the junction 204, and the holes (e.g., a hole 210) are collected by the substrate 208. When the electrons (e.g., an electron 212) generated due to the GIDL jump on a charge trapping layer 214 of the memory transistor 122, the electrons may program the memory transistor 122, which is not selected for programming, thus resulting in a programming error.
As the chip size gets smaller, the smaller channel length may create a short channel effect where the drain voltage of each transistor in the chip has more effect on the drain current than the gate to source voltage has. Accordingly, the short channel effect may contribute to the occurrence of the programming error due to the GIDL, which is another obstacle to the industry's effort for scaling down the chip size.